Not known Details About Anti-Tamper Digital Clocks
Not known Details About Anti-Tamper Digital Clocks
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17. The apparatus for detecting clock tampering as outlined in declare fifteen, whereby the Examine circuit is brought on by a clock edge at an finish of your clock evaluate period of time.
In other more comprehensive elements of the invention, Every with the plurality of delayed monotone alerts comprises either a a person or even a zero. The Consider circuit might figure out irrespective of whether the number of ones in the plurality of delayed monotone signals differs from the water level quantity by in excess of a predetermined threshold.
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33. The equipment for detecting voltage tampering as described in declare 30, whereby the usually means for assessing determines no matter whether the quantity of kinds during the plurality of delayed monotone signals differs from the water stage range by over a predetermined threshold.
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Exactly what is claimed is: 1. A way for detecting clock tampering, comprising: giving a plurality of resettable hold off line segments, wherein resettable delay line segments involving a resettable delay line section affiliated with a minimum amount delay time as well as a resettable hold off line segment associated with a utmost hold off time are Each and every connected with discretely increasing hold off situations;
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39. The equipment for detecting voltage tampering as outlined in declare 37, wherein the Examine circuit is activated by a clock edge at an conclude from the Consider period of time.
24. The strategy for detecting voltage tampering as described in declare 23, even further comprising: resetting the resettable delay line segments throughout a reset period of time, wherein the reset period of time is ahead of the Appraise time frame.
27. The method for detecting voltage tampering as defined in claim 26, wherein the h2o stage quantity is set depending on delayed monotone signals from one or more earlier Assess time.
A monotone sign is provided in the course of an Assess time period. The monotone sign is delayed employing Every with the plurality of resettable delay line segments to produce a respective plurality of delayed monotone signals. A clock is utilized to cause an Assess circuit that makes use of the plurality of delayed monotone indicators to detect a voltage fault.
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